3d integrated circuit system and method

ABSTRACT

A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

RELATED APPLICATIONS

This application is a divisional of and claims benefit of and priorityto application Ser. No. 12/209,478 entitled “3-D INTEGRATED CIRCUITSYSTEM AND METHOD” (Attorney Docket Number SPSN-AF02694), filed on Sep.12, 2008, which is hereby incorporated by this reference.

FIELD OF THE INVENTION

The present invention relates to the field of integrated circuit designand semiconductor chip fabrication. More particularly, the presentinvention relates to an efficient and effective system and method forfabricating three dimensional integrated circuits with multiple devicelayers.

BACKGROUND OF THE INVENTION

Electronic systems and circuits have made a significant contributiontowards the advancement of modern society and are utilized in a numberof applications to achieve advantageous results. Electronic technologiessuch as digital computers, calculators, audio devices, video equipment,and telephone systems have facilitated increased productivity andreduced costs in analyzing and communicating data, ideas and trends inmost areas of business, science, education and entertainment.Frequently, electronic systems designed to provide these results includeintegrated circuits. Integrated circuit fabrication usually involvesmulti-step processes that attempt to produce precise components. Manyintegrated circuit component fabrication processes involve complicatedinteractions that can have detrimental impacts on other componentswithin the integrated circuit. It can be very difficult to achieveoptimized results within requisite tolerances.

Semiconductor integrated circuit manufacturing efforts are usuallycomplicated by ever increasing demands for greater functionality. Morecomplicated circuits are usually required to satisfy the demand forgreater functionality. For example, there is usually a proportionalrelationship between the number of components included in an integratedcircuit and the functionality, integrated circuits with more componentstypically provide greater functionality. However, including morecomponents within an integrated circuit often requires the components tobe densely packed in relatively small areas and reliably packing a lotof components in relatively small areas of an IC is usually verydifficult. For example, as devices scale down to a 32 nm node or less,manufacturing becomes increasingly challenging due to fundamental limitssuch as defining such small structures.

Some traditional approaches have attempted to achieve greater densitiesby utilizing three dimensional integrated circuits with multiple layersof devices. However, achieving high quality single crystal silicon forthe upper layer devices has been a major roadblocks in the pursuit ofthree-dimensional multilayer device fabrication. Many integrated circuitdevices rely upon very precise building blocks (e.g., a single crystalsilicon region) for fabrication of reliable and proper operatingdevices. Conventional attempts at utilizing heat for annealing andcreating single crystal regions is a second layer device region aredifficult to implement because heat transfers to other layers areproblematic. Attempts at fabricating the layers as separate dies andthen combining them have also proved problematic due to lack of costeffective precise alignment techniques when mating the two separatelyfabricated portions.

SUMMARY OF THE INVENTION

A semiconductor fabrication system and method are presented. In oneembodiment of the present invention, a three dimensional multilayerintegrated circuit fabrication method includes forming a first devicelayer and forming a second device layer on top of the first device layerwith minimal detrimental heat transfer to the first layer by utilizing acontrolled laser layer formation annealing process. In one embodiment acontrolled laser crystallization process is utilized. In one exemplaryimplementation the controlled laser includes creating an amorphouslayer; defining a crystallization area in the amorphous layer, where inthe crystallization area is defined to prevent undesired heat transferto another layer; and applying laser to the crystallization area,wherein the laser is applied in a manner that prevents undesired heattransfer to another layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part ofthis specification, illustrate embodiments of the invention by way ofexample and not by way of limitation. The drawings referred to in thisspecification should be understood as not being drawn to scale except ifspecifically noted.

FIG. 1 is a flow chart of an exemplary three dimensional multilayerintegrated circuit fabrication method with multiple layers of devices inaccordance with one embodiment of the present invention.

FIG. 2 is a flow chart of an exemplary controlled laser crystallizationprocess in accordance with one embodiment of the present invention.

FIG. 3A is a block diagram of an exemplary first device layer inaccordance with one embodiment of the present invention prior tocreation of a second device layer.

FIG. 3B is a block diagram of an exemplary first device layer with asecond amorphous layer in accordance with one embodiment of the presentinvention.

FIG. 3C is a block diagram of an exemplary first device layer and seconddevice layer in accordance with one embodiment of the present invention.

FIG. 4 is a block diagram of an exemplary three dimensional multilayerintegrated circuit with multiple layers of devices in accordance withone embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of theinvention, a semiconductor isolation material deposition system andmethod, examples of which are illustrated in the accompanying drawings.While the invention will be described in conjunction with the preferredembodiments, it will be understood that they are not intended to limitthe invention to these embodiments. On the contrary, the invention isintended to cover alternatives, modifications and equivalents, which maybe included within the spirit and scope of the invention as defined bythe appended claims. Furthermore, in the following detailed descriptionof the present invention, numerous specific details are set forth inorder to provide a thorough understanding of the present invention.However, it will be obvious to one ordinarily skilled in the art thatthe present invention may be practiced without these specific details.In other instances, well known methods, procedures, components, andcircuits have not been described in detail as not to unnecessarilyobscure aspects of the current invention.

Convenient and efficient three dimensional multilayer integrated circuitsystems and methods with multiple layers of devices are presented. Athree dimensional multilayer integrated circuit system and method canfacilitate implementation of numerous devices in a single package with adensely packed configuration. In one embodiment, a controlled lasercrystallization process is utilized to form single crystal silicon forupper layers of a three dimensional integrated circuit with multiplelayers of devices. The application of lasers to controlled areasminimizes excess heat transfer to undesired regions.

FIG. 1 is a flow chart of three dimensional multilayer integratedcircuit fabrication method 100 with multiple layers of devices inaccordance with one embodiment of the present invention. In oneembodiment, three dimensional multiplayer integrated circuit fabricationmethod 100 facilitates fabrication of a plurality of device layers ontop of one another.

In block 110, a first device layer is formed. In one embodiment, deviceformation includes preparation of a silicon wafer, deposition ofisolation regions, etching predetermined patterns, and implantation ofactive regions. It is appreciated the first device layer can includemetal layers and interlayer dielectric layer. In one exemplaryimplementation, lithographic and etching techniques are utilized to inthe formation of the first device layer.

In block 120 a second device layer is formed on top of the first devicelayer without detrimental heat transfer to the first layer by utilizinga controlled laser crystallization process. In one embodiment, thecontrolled laser crystallization process creates a single crystal regionin the second device layer. In one exemplary implementation, thecontrolled laser crystallization process applies heat in a defined areaof the second layer without detrimental effects on the first layer. Forexample, the laser can be focused on a crystallization area the size ofa device, an array of devices, a predetermined size (e.g., 10 squaremicrometers, 200 square nanometers, etc.).

FIG. 2 is a flow chart of controlled laser crystallization process 200in accordance with one embodiment of the present invention. In oneembodiment, controller laser crystallization process 200 facilitatescrystallization of a single crystal silicon area. It is appreciated thatcontrolled laser crystallization processes can also be utilized inrecrystallization.

In block 210, an amorphous layer is created. In one embodiment, theamorphous layer includes an amorphous silicon region. In one exemplaryimplementation, the amorphous layer is included in an upper devicelayer. It is appreciated an amorphous layer can be created in a lowerdevice layer also. Seed growth from silicon in another layer can beutilized in the creation of the amorphous layer.

At block 220, a crystallization area is defined in the amorphous layer.The crystallization area is defined to promote single crystal growth(e.g., to prevent multi-crystalline growth). In one embodiment, thecrystallization area corresponds to a patterned active area and isformed before application of a laser. In one exemplary implementation,the crystallization area corresponds to a device area. The device can bea transistor. In one embodiment, the crystallization area can be up to10 square micrometers

In block 230, a laser is applied to the crystallization area. The laseris applied in a manner that prevents undesired heat transfer to anotherlayer. It is also appreciated the present invention can be implementedwith a variety of different lasers. In one embodiment, the laser canvary between a micrometer to a millimeter. In one exemplaryimplementation, patter laser crystallization is utilized.

It is appreciated that a number of techniques can be utilized to furtherenhance control of the laser application and corresponding heattransfer. In one embodiment, a coat layer is applied before applicationof the laser. The coat layer can be removed after the application of thelaser.

FIG. 3A is a block diagram of an exemplary first device layer 310 priorto creation of a second device layer. First device layer 310 includes asubstrate 311, active device areas 312 and 313, isolation trenches 314,315, and 316, and interlayer dielectric layer 317. The active deviceareas 312 and 313 and isolation trenches 314, 315 and 316 can be formedutilizing lithographic, etching, implantation and deposition techniques.

FIG. 3B is a block diagram of exemplary first device layer 310 with asecond amorphous layer 320. Second amorphous layer 320 is formed on topof first device layer 310. In one embodiment, second amorphous layer 320is grown utilizing a seed technique from silicon of first device layer310.

FIG. 3C is a block diagram of an exemplary first device layer 310 andsecond device layer 330. In one embodiment, second device layer 330 ispartially created in amorphous layer 320. Second device layer 330includes a single crystal area 331, active device areas 332 and 333,isolation trenches 334, 335, and 336, and interlayer dielectric layer337. The active device areas 332 and 333 and isolation trenches 334, 334and 336 can be formed utilizing techniques that are somewhat resistantto detrimental impact from heat transfer. In one embodiment, there canbe an amorphous 320B region that remains after crystallization.

It is appreciated that a variety of low temperature techniques can beutilized to correspond to a minimal thermal budget difference betweenthe top and bottom layers. In one embodiment, the bottom layer has extrathermal cycles for the top layer. In one embodiment SPA (Slotted PlasmaAntenna), LPRO (Low Pressure radical Oxidation), ISSG (In-situ steamgeneration) or ALD (Atomic Layer deposition) can be utilized in theformation of bottom oxide and top oxide. In one exemplary implementationthe SPA can be in the range of 400 C to 600 C, the LPRO in the range of650 C to 750 C, the ISSG in the range of 750 C to 800 C and the oxide inthe range of 600 C-700 C. In one embodiment SPA, ISSG, RTO or ALD can beutilized for IOX. In one exemplary implementation the SPA is in therange of 250 C to 400 C, the LPRO is in the range of 650 C to 650 C andthe H2O+H2 (RTO, rapid thermal oxidation) can be in the range of 650 Cto 850 C. It is also appreciated that for SD activation low temp RTAplus laser anneal can be utilized. In one embodiment the laser isutilized for activation.

It is also appreciated that additional techniques can be utilized tofurther facilitate reduction of detrimental impacts associated with heattransfer. In one embodiment, the techniques can include devices formedwith polysilicide gates and metal layers and metal connections betweendevices formed with material resistant to heat transfer affects (e.g.,tungsten, copper, etc.).

FIG. 4 is a block diagram of an exemplary three dimensional multilayerintegrated circuit 400 with multiple layers of devices in accordancewith one embodiment of the present invention. The dimensional multilayerintegrated circuit 400 includes a first device layer 410 with singlecrystal fabrication regions 411 and 412 and a second device layer 420with single crystal fabrication regions 421 and 422. The first devicelayer is coupled to the second device layer. In one embodiment, thesingle crystal fabrication regions of the second device layer are formedfrom silicon seed of the first device layer. The single crystalfabrication regions of the second layer can be defined by siliconisolation trenches and the single crystal fabrication regions are thesize of a transistor.

It is appreciated the present invention is compatible with a variety ofconfigurations. For example, the first layer can include peripheraldevices and the second layer comprises core devices. The first layer andthe second layer can include similar circuitry arrays. In oneembodiment, the first layer is utilized in association with a firstapplication and the second layer is utilized in association with asecond application.

Thus, a system and method of the present invention facilitatesfabrication and utilization of a three dimensional integrated circuitwith multiple device layers. The three dimensional integrated circuitcan accommodate densely packed devices. In one embodiment, the multipledevice layers can be formed with minimal detrimental impacts associatedwith undesired heat transfer.

The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteaching. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical application,to thereby enable others skilled in the art to best utilize theinvention and various embodiments with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the Claims appended hereto and theirequivalents.

1. A three dimensional multilayer integrated circuit comprising: a firstdevice layer with single crystal fabrication regions; and a seconddevice layer with single crystal fabrication regions, wherein saidsingle crystal fabrication regions of said second device layer areformed while said second layer is on top of said first layer, withminimal detrimental heat transfer to said first device layer utilizing acontrolled laser layer crystallization process for re-crystallization,wherein a crystallization area is defined to prevent undesired heattransfer between sad first device layer and said second device layer andsaid crystallization area is included in a single crystal fabricationregion of said second device layer formed from silicon seed of saidfirst device layer.
 2. A three dimensional multilayer integrated circuitof claim 1 wherein said single crystal fabrication regions of saidsecond device layer are formed from silicon seed of said first devicelayer.
 3. A three dimensional multilayer integrated circuit of claim 1wherein said single crystal fabrication regions of said second layer aredefined by silicon isolation trenches.
 4. A three dimensional multilayerintegrated circuit of claim 1 wherein said single crystal fabricationregions are the size of a transistor.
 5. A three dimensional multilayerintegrated circuit of claim 1 wherein said first layer comprisesperipheral devices and said second layer comprises core devices.
 6. Athree dimensional multilayer integrated circuit of claim 1 wherein saidfirst layer and said second layer comprise similar circuitry arrays. 7.A three dimensional multilayer integrated circuit of claim 1 whereinsaid first layer is utilized in association with a first application andsaid second layer is utilized in association with a second application.